ELEVATE SKILLS!
Enquiry FormRSSBRPSCUniversity of RajasthanRTU KotaCareers@SA
ELEVATE SKILLS!

CS Free MCQ Bank

Access a comprehensive computer science MCQ bank for free, featuring hundreds of questions with detailed solutions. Strengthen concepts, practice effectively, and prepare confidently for exams, quizzes, and competitive tests.

  • Home
  • CS MCQs
  • Computer Organization (COA)
  • I/O Organization and Interrupts MCQs+PYQs | DMA | Suraku Academy

Q: 1 Which of the following modes of I/O operation keeps the processor most busy?

  1. Programmed I/O

  2. Interrupt Initiated I/O

  3. DMA

  4. None of these

[ Option A ]

Input/Output (I/O) operations allow the CPU to communicate with external devices like keyboard, disk, printer, etc. There are three main I/O techniques:
1. Programmed I/O.
2. Interrupt-driven I/O.
3. DMA (Direct Memory Access).
In Programmed I/O, the CPU repeatedly checks the device status in a loop (called polling). During this time, the CPU cannot perform other useful tasks. This wastes processor time and keeps it fully occupied.
In Interrupt-driven I/O, the CPU performs other tasks and only responds when the device sends an interrupt signal. This reduces CPU idle waiting.
In DMA, a separate DMA controller handles data transfer directly between memory and the I/O device. The CPU is involved only at the beginning and end of the transfer. Therefore, CPU usage is minimal.

Q: 2 The technique where the controller is given complete access to main memory is ____________.

  1. Cycle Stealing

  2. Memory Stealing

  3. Memory Conditioning

  4. Burst Mode

[ Option D ]

In data transfer techniques like DMA (Direct Memory Access), the controller can transfer data between I/O device and main memory without CPU intervention.
In Burst Mode, the DMA controller is given complete control of the system bus and memory for a block of data transfer. During this time:

  • CPU is temporarily halted.
  • Entire data block is transferred in one continuous operation.
ModeWorking
Cycle StealingDMA takes control for one cycle at a time.
Burst ModeDMA takes full control until transfer completes.
Memory StealingSame as cycle stealing.

Q: 3 A CPU generally handles an interrupt by branching to the Interrupt Service Routine (ISR) pointed by interrupt table

  1. As soon as interrupt is raised by a peripheral.

  2. By checking the interrupt register at regular intervals of time

  3. By checking the interrupt register at the end of the current fetch cycle

  4. By checking the interrupt register after completing the current instruction execution

[ Option D ]

An interrupt is a signal that requests the CPU to stop its current work and execute a special routine called the Interrupt Service Routine (ISR).
However, the CPU does not stop immediately in the middle of an instruction. It follows a proper sequence to maintain correctness.

  • The CPU checks for interrupts only after completing the current instruction execution. This ensures that instructions are not left partially executed.

Q: 4 On receiving an interrupt from an I/O device, the CPUs:

  1. Hand over the control of address and data bus to interrupting device

  2. Branch off to interrupt service subroutine immediately

  3. Branch off to interrupt service subroutine after completion of current instruction

  4. None of these

[ Option C ]

An interrupt is a signal sent by an I/O device to the CPU to request immediate attention. However, the CPU does not stop execution in the middle of an instruction. When an interrupt occurs, the CPU first completes the execution of the current instruction to maintain correctness and consistency of operations. 
After finishing the current instruction, the CPU saves the necessary information and then branches to the Interrupt Service Routine (ISR) corresponding to that interrupt. This mechanism ensures proper control flow and prevents data corruption.

Q: 5 To access the I/O devices the status flags is continuously checked in:

  1. Program Controlled I/O

  2. Memory Mapped I/O

  3. I/O Mapped

  4. None of these

[ Option A ]

In Program Controlled I/O, the CPU continuously checks the status flags of the I/O device to see whether it is ready for data transfer. This method is also called polling, where the processor keeps testing the device status until the operation is complete.

Q: 6 When Bus Grant (BG) = 1 in Direct Memory Access (DMA) transfer, then what function read line and write lines perform?

  1. Read line and write act as input line allowing CPU to communicate with internal DMA register

  2. Read line act as input line and write line act as output line from DMA

  3. Read line act as output line and write line act as input line from DMA controller

  4. Read line and write line act as output line from DMA controller

[ Option D ]

In Direct Memory Access (DMA) transfer, the DMA controller temporarily takes control of the system bus from the CPU to transfer data directly between memory and I/O devices.
When Bus Grant (BG) = 1, it means the CPU has granted control of the bus to the DMA controller. After getting bus control, the DMA controller generates the required control signals itself.
Therefore, the Read Line and Write Line work as output lines from the DMA controller. These signals control memory read and write operations during DMA transfer.

Q: 7 The interrupt servicing mechanism in which the interrupt requesting device identifies itself to the processor is __________.

  1. Polling Mode

  2. Vectored Interrupts

  3. Nested Interrupts

  4. All the above

[ Option B ]

In interrupt handling, different mechanisms are used to identify which device has generated the interrupt.

  • In Vectored Interrupts, the interrupting device provides its own identification (vector address) to the CPU. This directly points to the appropriate Interrupt Service Routine (ISR).
  • In Polling Mode, the CPU checks each device one by one to find which one raised the interrupt. The device does not identify itself.
  • Nested Interrupts refer to handling multiple interrupts with priority, not identification.

Thank You for Reading!

Thank you so much for taking the time to read my Computer Science MCQs section carefully. Your support and interest mean a lot, and I truly appreciate you being part of this journey. Stay connected for more insights and updates! If you'd like to explore more tutorials and insights, check out my YouTube channel.

Don’t forget to subscribe and stay connected for future updates.