This section contains carefully selected MCQs and Previous Year Questions with explanations to help students understand concepts and prepare effectively for examinations, interviews, and competitive tests.
Q: 1Which of the following modes of I/O operation keeps the processor most busy?
Option A
Input/Output (I/O) operations allow the CPU to communicate with external devices like keyboard, disk, printer, etc. There are three main I/O techniques:
1. Programmed I/O.
2. Interrupt-driven I/O.
3. DMA (Direct Memory Access).
In Programmed I/O, the CPU repeatedly checks the device status in a loop (called polling). During this time, the CPU cannot perform other useful tasks. This wastes processor time and keeps it fully occupied.
In Interrupt-driven I/O, the CPU performs other tasks and only responds when the device sends an interrupt signal. This reduces CPU idle waiting.
In DMA, a separate DMA controller handles data transfer directly between memory and the I/O device. The CPU is involved only at the beginning and end of the transfer. Therefore, CPU usage is minimal.
Q: 2The technique where the controller is given complete access to main memory is ____________.
Option D
In data transfer techniques like DMA (Direct Memory Access), the controller can transfer data between I/O device and main memory without CPU intervention.
In Burst Mode, the DMA controller is given complete control of the system bus and memory for a block of data transfer. During this time:
| Mode | Working |
|---|---|
| Cycle Stealing | DMA takes control for one cycle at a time. |
| Burst Mode | DMA takes full control until transfer completes. |
| Memory Stealing | Same as cycle stealing. |
Q: 3Which of the following data transfer schemes requires constant monitoring by the CPU of the peripheral devices?
Option A
Input/Output (I/O) data transfer refers to the process of transferring data between the CPU, memory, and peripheral devices such as keyboard, mouse, printer, scanner, and hard disk.
There are three common I/O data transfer schemes:
In Programmed I/O, the CPU continuously checks the status of an input/output device to determine whether it is ready for data transfer.
This means the CPU must keep monitoring the device until the operation is completed. During this time, the CPU cannot efficiently perform other tasks, resulting in wastage of CPU time.
For example, if the CPU wants to receive data from a keyboard, it repeatedly checks whether a key has been pressed. This continuous checking is called Polling.
| Scheme | Description |
|---|---|
| Programmed I/O | The CPU continuously checks the status of the peripheral device to determine whether it is ready for data transfer. This method requires constant CPU monitoring (polling). |
| Interrupt-Driven I/O | The CPU starts the I/O operation and continues other work. When the device is ready, it sends an interrupt signal to notify the CPU. |
| Direct Memory Access (DMA) | A DMA controller transfers data directly between memory and the I/O device without continuous CPU involvement, resulting in faster data transfer and reduced CPU workload. |
Q: 4A CPU generally handles an interrupt by branching to the Interrupt Service Routine (ISR) pointed by interrupt table
Option D
An interrupt is a signal that requests the CPU to stop its current work and execute a special routine called the Interrupt Service Routine (ISR).
However, the CPU does not stop immediately in the middle of an instruction. It follows a proper sequence to maintain correctness.
Q: 5On receiving an interrupt from an I/O device, the CPUs:
Option C
An interrupt is a signal sent by an I/O device to the CPU to request immediate attention. However, the CPU does not stop execution in the middle of an instruction. When an interrupt occurs, the CPU first completes the execution of the current instruction to maintain correctness and consistency of operations.
After finishing the current instruction, the CPU saves the necessary information and then branches to the Interrupt Service Routine (ISR) corresponding to that interrupt. This mechanism ensures proper control flow and prevents data corruption.
Q: 6To access the I/O devices the status flags is continuously checked in:
Option A
In Program Controlled I/O, the CPU continuously checks the status flags of the I/O device to see whether it is ready for data transfer. This method is also called polling, where the processor keeps testing the device status until the operation is complete.
Q: 7When Bus Grant (BG) = 1 in Direct Memory Access (DMA) transfer, then what function read line and write lines perform?
Option D
In Direct Memory Access (DMA) transfer, the DMA controller temporarily takes control of the system bus from the CPU to transfer data directly between memory and I/O devices.
When Bus Grant (BG) = 1, it means the CPU has granted control of the bus to the DMA controller. After getting bus control, the DMA controller generates the required control signals itself.
Therefore, the Read Line and Write Line work as output lines from the DMA controller. These signals control memory read and write operations during DMA transfer.
Q: 8The interrupt servicing mechanism in which the interrupt requesting device identifies itself to the processor is __________.
Option B
In interrupt handling, different mechanisms are used to identify which device has generated the interrupt.
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