CS Free MCQ Bank

[ Option B ]

Pipelining is a technique in which a processor overlaps multiple stages of instruction execution. While one instruction is being executed, another instruction can be fetched and a third one can be decoded at the same time.
This means different stages like Fetch → Decode → Execute are performed simultaneously for different instructions, increasing CPU efficiency.

• Superscaling means executes multiple instructions in parallel using multiple pipelines, not stage overlapping.

[ Option A ]

In assembly language, addressing mode specifies how the operand is provided to the instruction.

In Immediate Addressing Mode, the operand is a constant value that is directly given in the instruction itself. It is not stored in a register or memory location.
In instruction MOV R1, #35H, #35H represents a constant hexadecimal value (35H). The # symbol indicates that the value is immediate data. This is immediate addressing mode because the value is directly provided in the instruction.

[ Option A ]

IA-32 (Intel Architecture, 32-bit) is a widely used computer architecture known for its support of a wide range of data types such as bytes (8 bits), words (16 bits), double words (32 bits), and quad words (64 bits).
It defines various data sizes and supports complex instruction sets for handling these different types efficiently, making it versatile across many computing applications.

[ Option D ]

Execution Time = (Number of Instructions) / (Instructions Per Second)
Number of instructions for program P= 2n²
Given, n=10000
Number of instructions = 2*(10000)² = 2*10⁸
Speed of computer is given as 10⁶ instructions per second.
Execution Time = (2*10⁸) / (10⁶) = 200 seconds

[ Option A ]

The Memory Address Register (MAR) is used to hold the address of the data that needs to be fetched from or stored to memory, including secondary memory locations during data transfer operations. 
When the CPU wants to fetch data from secondary memory, it places the address of the required data in the MAR, which then facilitates the transfer via the system bus.

• PC (Program Counter) keeps track of the next instruction.
• IR (Instruction Register) holds the current instruction.
• MBR (Memory Buffer Register) temporarily holds the data being transferred to or from memory.

[ Option C ]

A zero address instruction format means that the instruction does not explicitly specify any operands. Instead, all operations are performed using a stack, where operands are implicitly taken from the top of the stack.
In a stack-organized architecture, instructions like ADD automatically use the top elements of the stack, so no address fields are required.

[ Option B ]

In microprocessors like 8085, interrupts can be maskable or non-maskable. A Non-Maskable Interrupt (NMI) cannot be disabled or ignored by the processor and has the highest priority.
TRAP is a non-maskable interrupt, meaning:

• It cannot be masked (disabled).
• It is used for critical events like power failure.

[ Option B ]

When the CPU starts fetching or decoding the next instruction while the current instruction is still executing, this overlapping process is called Pipelining. It helps the CPU work faster by using its time efficiently.

[ Option A ]

The register that keeps track of the address of the next instruction to be executed is the Program Counter (PC). After one instruction is executed, the PC is automatically updated to point to the next instruction in memory.

[ Option A ]

In assembly language, instructions like MOV and ADD are called opcodes (Operation Codes). An opcode specifies what operation the processor has to perform, such as moving data or performing addition. An instruction generally has two parts:

• Opcode : Specifies the operation.
• Operand : Specifies the data or location on which operation is performed.

The operator is general programming term.

[ Option D ]

A Register is a very small and very fast memory unit inside the CPU. It is used to temporarily store data, instructions, addresses, or results while the CPU is working. Because registers are located inside the processor, the CPU can access them much faster than main memory (RAM).
An Index Register is a special-purpose register used mainly to modify the address of an operand during program execution. It is commonly used when accessing arrays, tables, or sequential data structures.

[ Option C ]

The Program Counter (PC) is a special register in the CPU that stores the address of the next instruction to fetch and execute from memory.
After fetching the current instruction, the PC increments to point to the next instruction’s address unless modified by a jump or branch instruction.
This allows the CPU to execute the sequence of instructions in order and supports control flow changes.

[ Option D ]

The CPU generates 32-bit virtual addresses. Since the page size is 4 KB, this means each page contains 2¹² bytes. Therefore, the lower 12 bits of the virtual address are used as the page offset. The remaining bits represent the virtual page number (VPN). Hence, the number of VPN bits is 32-12=20 bits.
The Translation Look-Aside Buffer (TLB) can hold a total of 128 page table entries and is 4-way set associative. This means the TLB is divided into sets, with each set containing 4 entries. The total number of sets in the TLB is 128/4=32. Since 32=2⁵, 5 bits are required to select a set.
The TLB tag is formed from the remaining bits of the virtual page number after removing the set index bits. Therefore, the size of the TLB tag is 20-5=15 bits.

[ Option B ]

Clock frequency = 2500 million cycles per second
= 2500*10⁶ = 2.5*10⁹ Hz
Clock period is the inverse of frequency:
Clock Period = 1/Clock Frequency
=1/2.5*10⁹ = 0.4*10⁻⁹ = 4.0*10⁻¹⁰ sec

Number Scale Table:

• Million : Mega : 10⁶
• Billion : Giga : 10⁹
• Trillion : Tera : 10¹²

[ Option D ]

The instruction fetch phase is the first step of the instruction cycle in a CPU. During this phase, the instruction is fetched from memory and prepared for execution.
During the instruction fetch phase, the address from the Program Counter (PC) is first transferred to the MAR, then the instruction is fetched from memory into the MDR, and finally it is transferred to the IR and decoded. 
The fetch phase ends when the instruction is placed in the IR and decoded, making it ready for execution.

[ Option A ]

Register Direct Addressing Mode

• In register direct addressing mode, the CPU directly accesses data stored in the processor’s registers.
• No memory fetch is required because the data is already inside a register.
• The instruction specifies the register name where the data is stored.
• This mode is fastest compared to memory or indirect addressing modes.

So, in Register Direct Addressing Mode, data are accessed by specifying the register name in which they are stored.

[ Option B ]

A Register is the smallest and fastest storage unit inside the CPU. Registers are located directly within the processor and are used to hold data, instructions, memory addresses, or intermediate results during execution.
Registers operate at the same speed as the CPU, which makes them significantly faster than cache and main memory. Because of their limited size and very high speed, they are used for immediate processing tasks.