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  • CPU Organization and Instruction Set MCQs | Addressing Modes | Suraku

Q: 1 Which of the following architecture is suitable for a wide range of data types?

  1. IA-32

  2. ARM

  3. ASUS firebird

  4. 68000

[ Option A ]

IA-32 (Intel Architecture, 32-bit) is a widely used computer architecture known for its support of a wide range of data types such as bytes (8 bits), words (16 bits), double words (32 bits), and quad words (64 bits).
It defines various data sizes and supports complex instruction sets for handling these different types efficiently, making it versatile across many computing applications.

Q: 2 Consider a computer system with speed of 106 instructions per second. A program P, having 2n2 steps is run on this system, where n is the input size. If n=10000, what is the execution time for P?

  1. 2 sec

  2. 20 sec

  3. 100 sec

  4. 200 sec

[ Option D ]

Execution Time = (Number of Instructions) / (Instructions Per Second)
Number of instructions for program P= 2n2
Given, n=10000
Number of instructions = 2*(10000)2 = 2*108
Speed of computer is given as 106 instructions per second.
Execution Time = (2*108) / (106) = 200 seconds

Q: 3 To fetch data from the secondary memory which one of the following registers is used?

  1. MAR

  2. PC

  3. IR

  4. MBR

[ Option A ]

The Memory Address Register (MAR) is used to hold the address of the data that needs to be fetched from or stored to memory, including secondary memory locations during data transfer operations. 
When the CPU wants to fetch data from secondary memory, it places the address of the required data in the MAR, which then facilitates the transfer via the system bus.

  • PC (Program Counter) keeps track of the next instruction.
  • IR (Instruction Register) holds the current instruction.
  • MBR (Memory Buffer Register) temporarily holds the data being transferred to or from memory.

Q: 4 The process when processor fetch or decode another instruction during the execution of current instruction is called?

  1. Supercomputing

  2. Pipelining

  3. Cloud Computing

  4. Grid Computing

[ Option B ]

When the CPU starts fetching or decoding the next instruction while the current instruction is still executing, this overlapping process is called Pipelining. It helps the CPU work faster by using its time efficiently.

Q: 5 Which of the following registers is used to keep track of address of memory location where the next instruction is located?

  1. Program Counter

  2. Memory Address Register

  3. Memory Data Register

  4. Instruction Counters

[ Option A ]

The register that keeps track of the address of the next instruction to be executed is the Program Counter (PC). After one instruction is executed, the PC is automatically updated to point to the next instruction in memory.

Q: 6 Index register in a digital computer is used for?

  1. Pointing to the stack address

  2. Indirect addressing

  3. Keeping track the number of times loop executed

  4. Address modification

[ Option D ]

A Register is a very small and very fast memory unit inside the CPU. It is used to temporarily store data, instructions, addresses, or results while the CPU is working. Because registers are located inside the processor, the CPU can access them much faster than main memory (RAM).
An Index Register is a special-purpose register used mainly to modify the address of an operand during program execution. It is commonly used when accessing arrays, tables, or sequential data structures.

REGISTER TYPEDESCRIPTION
Accumulator (AC)Stores intermediate results of arithmetic and logic operations.
Program Counter (PC)Holds the address of the next instruction to be executed.
Instruction Register (IR)Stores the instruction currently being executed.
Memory Address Register (MAR)Stores the address of the memory location to be accessed.
Memory Data Register (MDR)Stores data being transferred to or from memory.
General Purpose RegisterStore temporary data and operands.
Index RegisterUsed to modify addresses, especially while accessing arrays.
Base RegisterHolds the starting address of a program or data block
Stack Pointer (SP)Points to the top of the stack.
Status / Flag RegisterStores condition flags such as Zero, Carry, and Overflow.

Q: 7 Which Register holds the address of the next instruction to be executed?

  1. Instruction Register

  2. Accumulator

  3. Program Counter

  4. Data Register

[ Option C ]

The Program Counter (PC) is a special register in the CPU that stores the address of the next instruction to fetch and execute from memory.
After fetching the current instruction, the PC increments to point to the next instruction’s address unless modified by a jump or branch instruction.
This allows the CPU to execute the sequence of instructions in order and supports control flow changes.

Q: 8 A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128-page table entries and is 4-way set associative. The minimum size of the TLB tag is:

  1. 13 bits

  2. 20 bits

  3. 11 bits

  4. 15 bits

[ Option D ]

The CPU generates 32-bit virtual addresses. Since the page size is 4 KB, this means each page contains 212 bytes. Therefore, the lower 12 bits of the virtual address are used as the page offset. The remaining bits represent the virtual page number (VPN). Hence, the number of VPN bits is 32-12=20 bits.
The Translation Look-Aside Buffer (TLB) can hold a total of 128 page table entries and is 4-way set associative. This means the TLB is divided into sets, with each set containing 4 entries. The total number of sets in the TLB is 128/4=32. Since 32=25, 5 bits are required to select a set.
The TLB tag is formed from the remaining bits of the virtual page number after removing the set index bits. Therefore, the size of the TLB tag is 20-5=15 bits.

Q: 9 If a processor clock is rated as 2500 million cycles per second, then its clock period is?

  1. 2.50*10-10 sec

  2. 4.00*10-10 sec

  3. 1.00*10-10 sec

  4. None of these

[ Option B ]

Clock frequency = 2500 million cycles per second
= 2500*106 = 2.5*109 Hz
Clock period is the inverse of frequency:
Clock Period = 1/Clock Frequency
=1/2.5*109 = 0.4*10−9 = 4.0*10−10 sec

Number Scale Table:

NAMEPOWER OF 10
Thousand103
Million106
Billion109
Trillion1012
Quadrillion1015
Quintillion1018
  • Million : Mega : 106
  • Billion : Giga : 109
  • Trillion : Tera : 1012

Q: 10 In Register direct addressing mode, data are accessed by,

  1. specifying the register name in which they are stored.

  2. specifying the memory location in which they are stored.

  3. secondary storage.

  4. specifying the data directly.

[ Option A ]

Register Direct Addressing Mode

  • In register direct addressing mode, the CPU directly accesses data stored in the processor’s registers.
  • No memory fetch is required because the data is already inside a register.
  • The instruction specifies the register name where the data is stored.
  • This mode is fastest compared to memory or indirect addressing modes.

So, in Register Direct Addressing Mode, data are accessed by specifying the register name in which they are stored.

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