CS Free MCQ Bank

[ Option B ]

Pipelining is a technique in which a processor overlaps multiple stages of instruction execution. While one instruction is being executed, another instruction can be fetched and a third one can be decoded at the same time.
This means different stages like Fetch → Decode → Execute are performed simultaneously for different instructions, increasing CPU efficiency.

• Superscaling means executes multiple instructions in parallel using multiple pipelines, not stage overlapping.

[ Option A ]

In assembly language, addressing mode specifies how the operand is provided to the instruction.

In Immediate Addressing Mode, the operand is a constant value that is directly given in the instruction itself. It is not stored in a register or memory location.
In instruction MOV R1, #35H, #35H represents a constant hexadecimal value (35H). The # symbol indicates that the value is immediate data. This is immediate addressing mode because the value is directly provided in the instruction.

[ Option A ]

IA-32 (Intel Architecture, 32-bit) is a widely used computer architecture known for its support of a wide range of data types such as bytes (8 bits), words (16 bits), double words (32 bits), and quad words (64 bits).
It defines various data sizes and supports complex instruction sets for handling these different types efficiently, making it versatile across many computing applications.

[ Option B ]

An ‘m’ bit microprocessor means that it can process m bits of data at a time. This directly relates to the size of its data register, which must be capable of holding m bits.

[ Option D ]

Execution Time = (Number of Instructions) / (Instructions Per Second)
Number of instructions for program P= 2n²
Given, n=10000
Number of instructions = 2*(10000)² = 2*10⁸
Speed of computer is given as 10⁶ instructions per second.
Execution Time = (2*10⁸) / (10⁶) = 200 seconds

[ Option A ]

The Memory Address Register (MAR) is used to hold the address of the data that needs to be fetched from or stored to memory, including secondary memory locations during data transfer operations. 
When the CPU wants to fetch data from secondary memory, it places the address of the required data in the MAR, which then facilitates the transfer via the system bus.

• PC (Program Counter) keeps track of the next instruction.
• IR (Instruction Register) holds the current instruction.
• MBR (Memory Buffer Register) temporarily holds the data being transferred to or from memory.

[ Option C ]

A zero address instruction format means that the instruction does not explicitly specify any operands. Instead, all operations are performed using a stack, where operands are implicitly taken from the top of the stack.
In a stack-organized architecture, instructions like ADD automatically use the top elements of the stack, so no address fields are required.

[ Option B ]

In microprocessors like 8085, interrupts can be maskable or non-maskable. A Non-Maskable Interrupt (NMI) cannot be disabled or ignored by the processor and has the highest priority.
TRAP is a non-maskable interrupt, meaning:

• It cannot be masked (disabled).
• It is used for critical events like power failure.

[ Option C ]

In an instruction format, the total instruction size is fixed, and it must accommodate:

• Opcode to identify the instruction.
• Register operands.
• Immediate operand.

The instruction length is 32 bits. To represent 56 instructions, 6 bits are required for the opcode. 
Since there are 32 registers, each register needs 5 bits, so two registers require 10 bits. The remaining bits for the immediate operand are 32-(6+10) = 16 bits. As the immediate value is unsigned, its maximum value is 2¹⁶-1 = 65535.

[ Option D ]

The Program Counter (PC) is a special register in a processor that stores the address of the next instruction to be executed.
Normally, the Program Counter increases sequentially after each instruction. But some instructions change the normal flow of execution by loading a new address into the Program Counter.
The instructions that directly affect the Program Counter are:

• CALL
• JUMP (JMP)

These instructions transfer control from one location of the program to another.

• The CALL instruction is used to transfer program control to a subroutine or function.
• The JUMP instruction is used to transfer program control directly from one location to another location in the program.

[ Option C ]

In a computer, the operation code (opcode) is the part of an instruction that specifies which operation the CPU should perform, such as addition, subtraction, or data transfer.
If an opcode contains n bits, then each bit can have two possible values either 0 or 1. Therefore, the total number of different combinations possible with n bits is 2ⁿ.
Each unique combination can represent a different operation. Hence, a computer can perform 2ⁿ different operations.
For example, if value of n is 3 then total operations = 2³ = 8.

[ Option B ]

When the CPU starts fetching or decoding the next instruction while the current instruction is still executing, this overlapping process is called Pipelining. It helps the CPU work faster by using its time efficiently.

[ Option C ]

In PCB (Printed Circuit Board) manufacturing, different technologies are used to mount electronic components on the board. The cost of production depends on the manufacturing process, equipment required, assembly complexity, and component handling.
Through Hole Technology (THT) is considered the least expensive and simplest technology for basic PCB design and assembly, especially for small-scale production and educational projects.
In this technology, the leads of components are inserted through holes drilled in the PCB and then soldered on the opposite side.
In Surface Mount Technology (SMT), the components mounted directly on PCB surface and cost is high.

[ Option A ]

The register that keeps track of the address of the next instruction to be executed is the Program Counter (PC). After one instruction is executed, the PC is automatically updated to point to the next instruction in memory.

[ Option A ]

In assembly language, instructions like MOV and ADD are called opcodes (Operation Codes). An opcode specifies what operation the processor has to perform, such as moving data or performing addition. An instruction generally has two parts:

• Opcode : Specifies the operation.
• Operand : Specifies the data or location on which operation is performed.

The operator is general programming term.

[ Option D ]

A Register is a very small and very fast memory unit inside the CPU. It is used to temporarily store data, instructions, addresses, or results while the CPU is working. Because registers are located inside the processor, the CPU can access them much faster than main memory (RAM).
An Index Register is a special-purpose register used mainly to modify the address of an operand during program execution. It is commonly used when accessing arrays, tables, or sequential data structures.

[ Option C ]

The Program Counter (PC) is a special register in the CPU that stores the address of the next instruction to fetch and execute from memory.
After fetching the current instruction, the PC increments to point to the next instruction’s address unless modified by a jump or branch instruction.
This allows the CPU to execute the sequence of instructions in order and supports control flow changes.

[ Option A ]

In this question, the values are in hexadecimal. First, the instruction MOV BL, 8C loads 8C (hex) into BL, and MOV AL, 7E loads 7E (hex) into AL.

• 7E (Hex) = 126 (Decimal)
• 8C (Hex) = 140 (Decimal)

Now perform the addition:
126+140 = 266 (Decimal)
Convert 266 back to hexadecimal:
266 = 10A (Hex)
Since AL is an 8-bit register, it can store only values from 00 to FF (0 to 255 in Decimal). The result 10A (Hex) = 266 (Decimal) exceeds this range. 
So, AL stores only the lower 8 bits, which is 0A (Hex) = 10 (Decimal). The remaining higher bit (1) is carried out, so the carry flag is set.

[ Option D ]

The CPU generates 32-bit virtual addresses. Since the page size is 4 KB, this means each page contains 2¹² bytes. Therefore, the lower 12 bits of the virtual address are used as the page offset. The remaining bits represent the virtual page number (VPN). Hence, the number of VPN bits is 32-12=20 bits.
The Translation Look-Aside Buffer (TLB) can hold a total of 128 page table entries and is 4-way set associative. This means the TLB is divided into sets, with each set containing 4 entries. The total number of sets in the TLB is 128/4=32. Since 32=2⁵, 5 bits are required to select a set.
The TLB tag is formed from the remaining bits of the virtual page number after removing the set index bits. Therefore, the size of the TLB tag is 20-5=15 bits.

[ Option B ]

Clock frequency = 2500 million cycles per second
= 2500*10⁶ = 2.5*10⁹ Hz
Clock period is the inverse of frequency:
Clock Period = 1/Clock Frequency
=1/2.5*10⁹ = 0.4*10⁻⁹ = 4.0*10⁻¹⁰ sec

Number Scale Table:

• Million : Mega : 10⁶
• Billion : Giga : 10⁹
• Trillion : Tera : 10¹²

[ Option B ]

Addressing Modes define how an operand is specified in an instruction. In Immediate Addressing Mode, the actual data (operand) is directly provided within the instruction itself. This means no memory lookup is required to fetch the operand, making it fast and straightforward.
For example, in an instruction like MOV AL, 5, the value 5 is directly given in the instruction. Hence, it is called Immediate Addressing Mode.

[ Option C ]

During the fetch-execute cycle, specific CPU registers play important roles. The Program Counter (PC) holds the address of the next instruction to be fetched from memory. During the fetch phase, the PC is used to locate the instruction.
The fetched instruction is then loaded into the Instruction Register (IR), which holds the current instruction while it is being decoded and executed. So, both PC and IR are directly involved in the fetch and execute operations.
The Address Register (Memory Address Register [MAR]) is used to hold memory addresses during read/write operations, but it is not specifically responsible for controlling the fetch-execute sequence itself in this context.

[ Option C ]

During program execution, the CPU must keep track of which instruction is currently being executed and which one will be executed next. This is done using a special register called the Program Counter.
The Program Counter (PC) stores the memory address of the next instruction to be executed. As each instruction is executed, the PC is automatically updated to point to the next instruction in sequence. This ensures the correct flow of program execution.

[ Option D ]

The instruction fetch phase is the first step of the instruction cycle in a CPU. During this phase, the instruction is fetched from memory and prepared for execution.
During the instruction fetch phase, the address from the Program Counter (PC) is first transferred to the MAR, then the instruction is fetched from memory into the MDR, and finally it is transferred to the IR and decoded. 
The fetch phase ends when the instruction is placed in the IR and decoded, making it ready for execution.

[ Option B ]

In a microprocessor, the execution of an instruction is measured in T-states, where one T-state represents one clock cycle. The duration of each T-state depends on the clock frequency, which is derived from the crystal frequency.
In this question, the crystal frequency is 16 MHz, and since the clock operates at half of it, the effective clock frequency becomes 8 MHz. The time period of one clock cycle is the inverse of frequency, so one T-state takes 1/(8*10⁶) or 1/8 MHz = 0.125μs.
Now, the total time required to execute the instruction is given as 0.5 µs. To find the number of T-states, we divide the total execution time by the time of one T-state: 0.5/0.125 = 4. This means the instruction takes 4 clock cycles (T-states) to execute.

[ Option B ]

In a CPU, the opcode is the part of an instruction that specifies the operation to be performed. To uniquely represent all instructions, the number of opcode bits must be sufficient to encode every instruction.
In this question, the total number of instructions are 23 [20 (Arithmetic) + 1 (Control) + 2 (Data Transfer)].
To determine the minimum number of bits required, we use the concept that 2ⁿ possible combinations can be represented using n bits.
Here, 2⁴=16 is not enough to represent 23 instructions, while 2⁵=32 is sufficient. Therefore, the minimum number of bits required for the opcode is 5.

[ Option D ]

The Program Counter (PC) is a special register in the CPU that stores the address of the next instruction to be executed.
When the processor executes one instruction, the Program Counter automatically updates to point to the next instruction in memory. This helps the CPU execute programs sequentially.

• The current instruction stored in the Instruction Register (IR).

[ Option A ]

Register Direct Addressing Mode

• In register direct addressing mode, the CPU directly accesses data stored in the processor’s registers.
• No memory fetch is required because the data is already inside a register.
• The instruction specifies the register name where the data is stored.
• This mode is fastest compared to memory or indirect addressing modes.

So, in Register Direct Addressing Mode, data are accessed by specifying the register name in which they are stored.

[ Option B ]

A Register is the smallest and fastest storage unit inside the CPU. Registers are located directly within the processor and are used to hold data, instructions, memory addresses, or intermediate results during execution.
Registers operate at the same speed as the CPU, which makes them significantly faster than cache and main memory. Because of their limited size and very high speed, they are used for immediate processing tasks.