This section contains carefully selected MCQs and Previous Year Questions with explanations to help students understand concepts and prepare effectively for examinations, interviews, and competitive tests.
Q: 1A processor performing fetch or decoding of different instruction during the execution of another instruction is called ___________.
Option B
Pipelining is a technique in which a processor overlaps multiple stages of instruction execution. While one instruction is being executed, another instruction can be fetched and a third one can be decoded at the same time.
This means different stages like Fetch → Decode → Execute are performed simultaneously for different instructions, increasing CPU efficiency.
Q: 2Which of the following obeys immediate addressing mode in assembly language (R1 and R2 are registers)?
Option A
In assembly language, addressing mode specifies how the operand is provided to the instruction.
In Immediate Addressing Mode, the operand is a constant value that is directly given in the instruction itself. It is not stored in a register or memory location.
In instruction MOV R1, #35H, #35H represents a constant hexadecimal value (35H). The # symbol indicates that the value is immediate data. This is immediate addressing mode because the value is directly provided in the instruction.
Q: 3Which of the following architecture is suitable for a wide range of data types?
Option A
IA-32 (Intel Architecture, 32-bit) is a widely used computer architecture known for its support of a wide range of data types such as bytes (8 bits), words (16 bits), double words (32 bits), and quad words (64 bits).
It defines various data sizes and supports complex instruction sets for handling these different types efficiently, making it versatile across many computing applications.
Q: 4Which of the following is correct for an ‘m’ bit microprocessor?
Option B
An ‘m’ bit microprocessor means that it can process m bits of data at a time. This directly relates to the size of its data register, which must be capable of holding m bits.
| Statement | Why Incorrect? |
|---|---|
| It has m-1 bits Instruction Register | Instruction register size depends on instruction format, not fixed as m-1. |
| It has m-1 bit Data Register | Data register must be m bits to match processor word size. |
| It must have m bit Flag Register | Flag register size depends on number of flags, not on m. |
Q: 5Consider a computer system with speed of 106 instructions per second. A program P, having 2n2 steps is run on this system, where n is the input size. If n=10000, what is the execution time for P?
Option D
Execution Time = (Number of Instructions) / (Instructions Per Second)
Number of instructions for program P= 2n2
Given, n=10000
Number of instructions = 2*(10000)2 = 2*108
Speed of computer is given as 106 instructions per second.
Execution Time = (2*108) / (106) = 200 seconds
Q: 6To fetch data from the secondary memory which one of the following registers is used?
Option A
The Memory Address Register (MAR) is used to hold the address of the data that needs to be fetched from or stored to memory, including secondary memory locations during data transfer operations.
When the CPU wants to fetch data from secondary memory, it places the address of the required data in the MAR, which then facilitates the transfer via the system bus.
Q: 7Zero address instruction format is used for ___________.
Option C
A zero address instruction format means that the instruction does not explicitly specify any operands. Instead, all operations are performed using a stack, where operands are implicitly taken from the top of the stack.
In a stack-organized architecture, instructions like ADD automatically use the top elements of the stack, so no address fields are required.
Q: 8Which of the following sequences of one-address instructions can be used to evaluate Y=(A-B)/(C+D*E)?
Option A
In a one-address instruction format, one operand is explicitly specified, while the other operand is assumed to be in the Accumulator (AC). Operations are performed using the accumulator, and intermediate results are often stored in memory.
The given expression is Y=(A-B)/(C+D*E).
To evaluate this expression, we first compute the denominator (C+D*E), store it temporarily, then compute the numerator (A-B), divide the numerator by the stored denominator, and finally store the result in Y.
Execution Table:
| Step | Instruction | Operation Performed | Accumulator (AC) Content |
|---|---|---|---|
| 1 | LOAD D | Load D into AC | D |
| 2 | MPY E | Multiply D by E | D*E |
| 3 | ADD C | Add C to AC | C+D*E |
| 4 | STORE Y | Store denominator in Y | Y = C+D*E |
| 5 | LOAD A | Load A into AC | A |
| 6 | SUB B | Subtract B from AC | A-B |
| 7 | DIV Y | Divide by stored denominator | (A-B)/(C+D*E) |
| 8 | STORE Y | Store final result in Y | Y = (A-B)/(C+D*E) |
Q: 9Which of the interrupts are non-maskable?
Option B
In microprocessors like 8085, interrupts can be maskable or non-maskable. A Non-Maskable Interrupt (NMI) cannot be disabled or ignored by the processor and has the highest priority.
TRAP is a non-maskable interrupt, meaning:
Q: 10A processor has 32bit architecture with 32 bit word instructions. It has 32 registers of each 32 bits long. It need to support 56 instructions, which have immediate operand in addition to two register operands. Assume that the immediate operand is an unsigned integer, the maximum value of immediate operand is?
Option C
In an instruction format, the total instruction size is fixed, and it must accommodate:
The instruction length is 32 bits. To represent 56 instructions, 6 bits are required for the opcode.
Since there are 32 registers, each register needs 5 bits, so two registers require 10 bits. The remaining bits for the immediate operand are 32-(6+10) = 16 bits. As the immediate value is unsigned, its maximum value is 216-1 = 65535.
Q: 11Program Counter gets effected by which instruction?
Option D
The Program Counter (PC) is a special register in a processor that stores the address of the next instruction to be executed.
Normally, the Program Counter increases sequentially after each instruction. But some instructions change the normal flow of execution by loading a new address into the Program Counter.
The instructions that directly affect the Program Counter are:
These instructions transfer control from one location of the program to another.
Q: 12When n bits are used to represent an operation (op) code, then how many different operations a computer can perform?
Option C
In a computer, the operation code (opcode) is the part of an instruction that specifies which operation the CPU should perform, such as addition, subtraction, or data transfer.
If an opcode contains n bits, then each bit can have two possible values either 0 or 1. Therefore, the total number of different combinations possible with n bits is 2n.
Each unique combination can represent a different operation. Hence, a computer can perform 2n different operations.
For example, if value of n is 3 then total operations = 23 = 8.
Q: 13The process when processor fetch or decode another instruction during the execution of current instruction is called?
Option B
When the CPU starts fetching or decoding the next instruction while the current instruction is still executing, this overlapping process is called Pipelining. It helps the CPU work faster by using its time efficiently.
Q: 14The least expensive technology is for PCB design is
Option C
In PCB (Printed Circuit Board) manufacturing, different technologies are used to mount electronic components on the board. The cost of production depends on the manufacturing process, equipment required, assembly complexity, and component handling.
Through Hole Technology (THT) is considered the least expensive and simplest technology for basic PCB design and assembly, especially for small-scale production and educational projects.
In this technology, the leads of components are inserted through holes drilled in the PCB and then soldered on the opposite side.
In Surface Mount Technology (SMT), the components mounted directly on PCB surface and cost is high.
Q: 15Which of the following registers is used to keep track of address of memory location where the next instruction is located?
Option A
The register that keeps track of the address of the next instruction to be executed is the Program Counter (PC). After one instruction is executed, the PC is automatically updated to point to the next instruction in memory.
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