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  • Computer Architecture Miscellaneous MCQs + PYQs | Suraku Academy

Q: 1 The following are the characteristics considered while deciding a processor architecture
(i)   Register to register arithmetic operations only.
(ii)  Fixed length instruction format.
(iii)  Hardwired control unit.
(iv)  Variable length instruction format.
Which of the above characteristics are applied in the design of RISC processor?

  1. (i) and (ii) only

  2. (i), (ii) and (iv) only

  3. (i), (ii) and (iii) only

  4. (i), (ii) and (iv) only

[ Option C ]

A RISC (Reduced Instruction Set Computer) architecture is designed to simplify instructions and improve execution speed. Its main characteristics include:

  • Simple and fast instructions.
  • Use of registers for operations.
  • Fixed instruction format.
  • Fast control using hardwired logic.
STATEMENTRISC APPLICABLE?EXPLANATION
Register to register arithmetic operations onlyYesRISC uses load/store architecture. Operations are performed on registers only.
Fixed length instruction formatYesHelps in fast instruction decoding and pipelining.
Hardwired control unitYesProvides faster execution compared to microprogrammed control.
Variable length instruction formatNoThis is a feature of CISC, not RISC.

Q: 2 Register renaming is done in pipelined processors -

  1. As an alternative to register allocation at compile time

  2. For efficient access to function parameters and local variables

  3. To handle certain kinds of hazards

  4. As part of address translation

[ Option C ]

Register renaming is a technique used in modern superscalar and pipelined processors to eliminate a specific type of data hazard called WAR (Write-After-Read) and WAW (Write-After-Write) hazards. These are also known as "Name Dependencies" because they arise not from a true data dependency, but from the reuse of a limited number of architectural registers.

  • WAR Hazard: A later instruction tries to read an old value from a register that a previous instruction is about to overwrite.
  • WAW Hazard: A later instruction tries to write to a register before an earlier instruction that also writes to the same register has completed.

Q: 3 The instruction pipeline in a RISC processor has the following stages, such as Instruction Fetch, Instruction Decode, Operand Fetch, Perform Operation and Write Back. All stages take only 1 clock cycle except Perform Operation stage. When a program of 150 instructions is executed, in Perform Operation stage 60 instructions take 3 clock cycles, 50 instructions take 2 clock cycles and the remaining instructions take 1 clock cycle. Total number of clock cycles required for the completion of the sequence of instructions is

  1. 644

  2. 320

  3. 324

  4. 524

[ Option C ]

In a Pipeline Processor, multiple instructions are executed in an overlapping manner. The total number of clock cycles required is given by:

  • Total Cycles = Number of Instructions + (Number of Pipeline Stages - 1) + Extra Cycles (Due to Delays/Stalls)

If any stage takes more than 1 cycle for some instructions, it causes pipeline stalls, which increase total execution time.
Step 1: Base Pipeline Cycles

  • Number of Instructions = 150
  • Number of Stages = 5
  • Base Cycles = 150 + (5 - 1) = 154

Step 2: Extra Cycles (Perform Operation Stage)
Normal Time = 1 Cycle, so extra delay:

  • 60 instructions take 3 cycles instead of 1, so extra = 60*2=120
  • 50 instructions take 2 cycles instead of 1, so extra = 50*1=50
  • Remaining 40 instructions take 1 cycle, so extra = 0

Total Extra Cycles = 120+50 = 170
Step 3: Total Clock Cycles

  • Total Cycles = 154+170 = 324

Q: 4 Consider a 4-segment pipeline with a clock cycle time 25 ns in each sub operation. Find out the speed-up ratio between pipelined and non-pipelined system to execute 50 instructions without stall conditions.

  1. 5.0

  2. 4.0

  3. 3.77

  4. 4.81

[ Option C ]

In pipelining, multiple instructions are executed in an overlapping manner. The speed-up is calculated as:
Speed-Up = Time Without Pipelining / Time With Pipelining
First, for Non-Pipelined Execution:

  • There are 4 stages and each stage takes 25 ns, so time per instruction = 4*25 = 100 ns.
  • For 50 instructions, total time = 50*100 = 5000 ns.

Now, for Pipelined Execution:

  • Total Time = (k+n -1)*T
  • Where k = 4 stages, n = 50 instructions, T = 25 ns
  • So, Total Time = (4+50-1)*25 = 53*25 = 1325 ns

Finally, Speed-Up = 5000/1325 = 3.77

Q: 5 Which of the following is true about CISC architecture?
(I)    Large code size.
(II)   Reduced instruction set.

  1. Both I and II

  2. Neither I Nor II

  3. Only I

  4. Only II

[ Option C ]

CISC stands for Complex Instruction Set Computer. It is a processor architecture design that uses a large and complex set of instructions.
CISC Processors:

  • Have many complex instructions.
  • Support multiple addressing modes.
  • Often use variable-length instructions.
RISC (Reduced Instruction Set Computer)CISC (Complex Instruction Set Computer)
Uses a small and simple instruction set.Uses a large and complex instruction set.
Simpler hardware design.More complex hardware design.
Each instruction usually executes in one clock cycle.Instructions may take multiple clock cycles.
Fixed-length instructions.Variable-length instructions.
Fewer addressing modes.Many addressing modes.
Lower power consumption.Higher power consumption.
Follows Load/Store architecture.Allows memory-to-memory operations.
Easier and more efficient pipelining.Pipelining is more complex due to variable instruction size.
Higher dependence on compiler optimization.Lower dependence on compiler optimization.
Examples: ARM, MIPS, SPARCExamples: Intel x86, VAX
  • ARM : Advanced RISC Machine.
  • MIPS : Microprocessor without Interlocked Pipeline Stages.
  • SPARC : Scalable Processor Architecture.
  • VAX : Virtual Address eXtension.

Q: 6 In a pipelined processor the situation in which the data for the operands are not yet ready for use, is an example of

  1. Data Blockage

  2. Data Hazard

  3. Deadlock

  4. Structural Hazard

[ Option B ]

In a Pipelined Processor, multiple instructions are executed simultaneously in different stages. Sometimes, an instruction needs data that is not yet available because a previous instruction has not completed. This situation is called a Data Hazard.

Q: 7 Performance of a pipeline processor suffers if

  1. The pipelines stages have different delays

  2. Consecutive instructions are dependent on each other

  3. Pipelines stages share hardware resources

  4. All the above

[ Option D ]

A Pipeline Processor improves performance by executing multiple instructions in overlapping stages. However, its performance can degrade due to several types of hazards or inefficiencies.

  • When pipeline stages have different delays, the overall speed is limited by the slowest stage. Faster stages have to wait, which reduces efficiency.
  • When consecutive instructions are dependent on each other, the next instruction cannot proceed until the previous one completes, causing pipeline stalls.
  • When pipeline stages share hardware resources, conflicts occur, and some instructions must wait, reducing throughput.

All these situations introduce delays or stalls in the pipeline, which negatively affect performance.

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