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Q: 1 Register renaming is done in pipelined processors -

  1. As an alternative to register allocation at compile time

  2. For efficient access to function parameters and local variables

  3. To handle certain kinds of hazards

  4. As part of address translation

[ Option C ]

Register renaming is a technique used in modern superscalar and pipelined processors to eliminate a specific type of data hazard called WAR (Write-After-Read) and WAW (Write-After-Write) hazards. These are also known as "Name Dependencies" because they arise not from a true data dependency, but from the reuse of a limited number of architectural registers.

  • WAR Hazard: A later instruction tries to read an old value from a register that a previous instruction is about to overwrite.
  • WAW Hazard: A later instruction tries to write to a register before an earlier instruction that also writes to the same register has completed.

Q: 2 Which of the following is true about CISC architecture?
(I)    Large code size.
(II)   Reduced instruction set.

  1. Both I and II

  2. Neither I Nor II

  3. Only I

  4. Only II

[ Option C ]

CISC stands for Complex Instruction Set Computer. It is a processor architecture design that uses a large and complex set of instructions.
CISC Processors:

  • Have many complex instructions.
  • Support multiple addressing modes.
  • Often use variable-length instructions.
RISC (Reduced Instruction Set Computer)CISC (Complex Instruction Set Computer)
Uses a small and simple instruction set.Uses a large and complex instruction set.
Simpler hardware design.More complex hardware design.
Each instruction usually executes in one clock cycle.Instructions may take multiple clock cycles.
Fixed-length instructions.Variable-length instructions.
Fewer addressing modes.Many addressing modes.
Lower power consumption.Higher power consumption.
Follows Load/Store architecture.Allows memory-to-memory operations.
Easier and more efficient pipelining.Pipelining is more complex due to variable instruction size.
Higher dependence on compiler optimization.Lower dependence on compiler optimization.
Examples: ARM, MIPS, SPARCExamples: Intel x86, VAX
  • ARM : Advanced RISC Machine.
  • MIPS : Microprocessor without Interlocked Pipeline Stages.
  • SPARC : Scalable Processor Architecture.
  • VAX : Virtual Address eXtension.

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