CS Free MCQ Bank

[ Option C ]

A memory unit stores data in the form of words. Each word contains a fixed number of bits. The total capacity of a memory is therefore defined as:
Memory Capacity=Number of words × Number of bits per word
To access and transfer data between the CPU and memory, two types of lines are used:

• Address lines which are used to select a specific memory word or location.
• Data lines which are used to transfer data to or from the selected memory word.

The Given Memory : 4K * 16
4K represents the number of words in memory : 4K = 4*1024 = 4096 Words.
16 represents the number of bits per word.
Each memory word must have a unique address. The number of address lines required depends on how many different addresses must be generated or number of memory locations (words).
Number of address lines = log₂(Number of Words)
=log₂(4096) = 12 or 4096=2¹²
The memory needs 12 address lines to uniquely identify all 4096 words.
Data lines are used to read or write one complete word at a time. Since each word contains 16 bits, the memory must have 16 data lines.

NOTE:

• Number of address lines = log₂(number of words).
• Number of data lines = decided by word size (bits per word).

[ Option B ]

A disk cache stores frequently accessed data in fast memory (RAM) to reduce slow disk I/O operations.
Hit Rate is the probability a requested data block is found in cache (40% here). Cache access time (1 ms) is much faster than disk access time (100 ms). Mean Access Time (MAT) combines both using the formula: 
MAT = (Hit Rate*Cache Time) + ((1-Hit Rate)*Disk Time)
With cache access time of 1 ms, disk access time of 100 ms, and 40% hit rate, the mean access time calculates as: 
MAT = (0.4*1)+(0.6*100) = 0.4+60 = 60.4 ms.

[ Option C ]

In computer architecture, locality of reference describes how programs access memory. One important type is spatial locality, which means that if a particular memory location is accessed, then nearby memory locations are likely to be accessed soon.
For example, when accessing elements of an array sequentially, once one element is accessed, the next nearby elements are also accessed.

[ Option B ]

An I/O processor is a special-purpose processor used to handle input and output operations independently of the CPU. Its main job is to manage data transfer between I/O devices and Main Memory.
By doing this, the I/O processor reduces the workload on the CPU and allows the CPU to continue executing other instructions while I/O operations are in progress.

[ Option A ]

SRAM (Static Random Access Memory) is the most expensive memory among SRAM, DRAM, and ERAM because it is faster, more reliable, and does not require refreshing repeatedly like DRAM.
SRAM uses more transistors for storing each bit, which increases its manufacturing cost. It is commonly used in Cache Memory.

[ Option A ]

In a RAM chip, the number of address lines determines the number of memory locations, while the number of data lines determines how many bits are stored in each location.
Here, the number of address lines is 10, so the total number of memory locations is 2¹⁰. The number of data lines is 8, which means each location can store 8 bits. Since 8 = 2³, each location stores 2³ bits.
Therefore, the total memory capacity of the RAM chip is 2¹⁰ * 2³ = 2¹³ bits.

[ Option D ]

In a Virtual Memory system, the CPU generates addresses based on its address lines, which define the virtual address space. This virtual address space represents the range of memory addresses that a program can use, and it is not limited to the size of the physical main memory (RAM).
One of the main purposes of virtual memory is to allow programs to use an address space that is larger than the available physical memory, with the extra portion being stored on secondary storage.
However, the virtual address space cannot exceed the size of the secondary storage, because secondary storage is where the non-resident pages of memory are actually stored.
Therefore, the address space specified by the CPU must be larger than the physical memory size but smaller than the secondary storage size.

• Virtual Address Space > Physical Memory (RAM).
• Virtual Address Space < Secondary Storage (HDD).

[ Option C ]

Each RAM chip is of size 32K × 1. This means, 32K locations and 1 bit per location. So, capacity of one chip is 32K*1 bit=32K bits.
Required memory capacity : 256K bytes = 256K*8 = 2048K bits
Number of chips required : 2048K bits/32K bits per chip = 64

[ Option C ]

Cache Memory is used to store frequently accessed data so that the CPU can access it faster than main memory.
In direct mapping, each block of main memory is mapped to exactly one fixed location (line) in the cache.
This fixed mapping makes the design simple and inexpensive, but it also introduces a major drawback known as the conflict problem. 
When two or more frequently accessed main memory blocks are mapped to the same cache line, they continuously replace each other in the cache. 
As a result, even though the blocks are repeatedly used, they cannot remain in the cache simultaneously. This frequent replacement reduces the cache hit ratio and degrades overall performance.

[ Option C ]

Cache Mapping determines how memory blocks are placed in cache. In Direct Mapping, each memory block is mapped to exactly one specific cache block using a fixed formula.
In this method, consecutive memory blocks are mapped to consecutive cache blocks in a cyclic manner. This makes the mapping simple and fast.

[ Option D ]

In Cache Memory, LRU (Least Recently Used) is a replacement policy used to decide which block should be removed when a new block needs to be inserted. 
Each cache block is assigned a counter to track how recently it was used. The block with the highest counter is least recently used.
In LRU, when the requested block is not already in cache, a new block is brought in, its counter becomes 0, and the other counters are incremented. That is exactly the Miss case, not hit or write. 
The wording “a new block is identified” points to the moment a block is loaded into the cache, which happens on a Miss.

[ Option B ]

Cache Memory works effectively because of the locality of reference principle. This means that programs tend to access the same data or instructions repeatedly (Temporal Locality) or access nearby memory locations (Spatial Locality). Cache stores such frequently or recently used data, so the CPU can access it much faster than main memory.

[ Option B ]

The number of address lines depends on how many unique memory locations (words) need to be addressed. Here, the memory stores 8K words, and each word is 16 bits, but word size does not affect the number of address lines, only the number of locations matters.
So, 8K = 8*1024 = 8192 Locations. To find the number of address lines n, we use:
2ⁿ=8192
2¹³=8192
So, 13 address lines are required.

[ Option C ]

Access time refers to how quickly data can be read from memory. Among the given options, Cache Memory has the shortest access time because it is located very close to the CPU and is designed for high-speed operations.
Cache stores frequently used data and instructions so that the CPU can access them quickly without going to slower memory levels. Its access time is even faster than RAM.
The general speed order from fastest to slowest is:
Registers > Cache > RAM > SSD > HDD (Disk) > USB (Flash Drive)

• Registers are inside the CPU, so they are the fastest.
• Cache is very close to the CPU and stores frequently used data.
• RAM is main memory, slower than cache but still fast.
• SSD is faster than traditional disks due to no moving parts.
• HDD (Disk) is slower because it uses mechanical parts.
• USB is external storage and generally slower in access time.

[ Option B ]

[ Option A ]

In cache memory systems, when the CPU writes data, there are different policies to decide how memory is updated.
In the WRITE-THROUGH policy, whenever data is written to the cache, the same data is immediately written to the main memory as well. This ensures that both cache and main memory always remain consistent.
So, if a memory write operation updates both cache and main memory at the same time, it is called Write-through.

[ Option D ]

The maximum memory that can be accessed depends on the number of address lines. If there are n address lines, then the total number of unique addresses that can be generated is 2ⁿ.
Here, number of address lines are 16, so total memory locations are 2¹⁶=65536 locations. Each location typically stores 1 byte, so total memory are 65536 bytes = 64KB.

[ Option D ]

Memory Interlacing (Memory Interleaving) is a technique in which main memory is divided into several independent modules (banks) and addresses are distributed across them in a round‑robin fashion.
When the CPU accesses memory, different banks can be accessed in parallel or overlapped, so the next piece of data is already being read from another bank while the previous one is being processed. This improves memory bandwidth and reduces effective access time, which is perceived as higher effective speed of memory.

[ Option C ]

Computer memory forms a hierarchy based on speed, cost, and capacity. Faster memory sits closer to the CPU for quick access during instruction execution, while slower memory holds bulk data. 
Registers are the tiniest, fastest storage inside the CPU itself. They store small amounts of data such as operands, instructions, and intermediate results, allowing very high-speed operations.

[ Option D ]

Effective Memory Access Time (EMAT) depends on how often data is found in the cache (hit) and how often it must be fetched from main memory (miss).
Given:

• Main memory access time = 10 milliseconds
• Cache access time = 10 microseconds = 0.01 milliseconds
• Cache hit ratio = 15% = 0.15
• Miss ratio = 1-0.15 = 0.85

EMAT = (Hit Ratio*Cache Access Time) + (Miss Ratio*Main Memory Access Time)
EMAT = (0.15*0.01 ms) + (0.85*10 ms)
EMAT = 0.0015 ms + 8.5 ms
EMAT = 8.5015 ms = 1.85 milliseconds.

[ Option A ]

The CPU can directly access only one type of memory, which is the memory used to store programs and data that are currently being executed. This type of memory is called Primary Memory or Main Memory or RAM.

[ Option C ]

Memory capacity is represented in the form of:
Number of Memory Locations * Number of Bits per Location
A RAM chip of 16K * 1 bit means the chip contains 16K memory locations and each location can store 1 bit of data.
The required memory capacity is 128K * 1 byte. Since 1 byte = 8 bits, the required memory becomes 128K * 8 bits.
Now divide the required memory capacity by the capacity of one RAM chip, 128K*8 / 16K*1 = 64.
Therefore, 64 RAM chips are required to provide a memory capacity of 128K * 1 byte.

[ Option B ]

In computer organization, the number of address lines determines how many unique memory locations can be accessed. If there are n address lines, then the total number of addressable memory locations is given by: 2ⁿ.

• Each additional address line doubles the number of possible addresses.

When the number of address lines is increased from n to (n+1), the total memory locations become: 2ⁿ⁺¹ = 2*2ⁿ. This means the memory capacity becomes twice the original.

[ Option B ]

In memory organization, the number of address lines depends on how many unique memory locations need to be accessed. If a memory chip has N locations, then the number of address lines required is:
Address Lines = log₂(N)
In the given memory chip 2048*4, 2048 represents the number of memory locations and 4 represents the number of bits per location, which is not relevant for address lines. 
Since 2048 = 2¹¹, a total of 11 address lines are required to uniquely access all memory locations.

[ Option C ]

In computer architecture, memory refers to components that store data or instructions.

• Instruction Cache is a type of cache memory that stores frequently used instructions for fast access. 
• The Instruction Register (IR) is a CPU register that temporarily holds the current instruction being executed, so it is also a form of storage. 
• The Translation Look-aside Buffer (TLB) is a special memory that caches recent address translations to speed up virtual memory access.

However, an instruction op-code is not a memory unit. It is just a part of an instruction that specifies the operation to be performed like ADD, SUB, etc.

[ Option D ]

Address Lines in Memory

• Each memory location in a computer is assigned a unique address.
• To access these memory locations, the system uses address lines.
• The number of address lines determines how many unique locations can be addressed.
• If there are n address lines, the total number of memory locations = 2ⁿ.

Given: Memory size = 512 bytes
Number of address lines n is calculated using:
2ⁿ = Memory size in bytes
2ⁿ = 512
Since 2⁹=512, we find n=9.

[ Option B ]

The bandwidth of memory tells us how many memory accesses can be completed per second. To find this, we must first calculate the total time required for one complete memory cycle.
Given,
Access time = 45ns
Time gap before next access = 5ns
Total Cycle Time : 45ns + 5ns = 50ns
Bandwidth is the reciprocal of the cycle time: 
Bandwidth : 1 / (Access Time + Recovery Time)
Bandwidth : 1/(50*10^-9) Since : 1ns = 10^-9 seconds
Bandwidth : 1000*10⁶/50 = 20*10⁶ Hz
Bandwidth : 20 MHz

Time and Frequency Units:

• Pico, nano, micro, and milli are commonly used for time, while kilo, mega, giga, and tera are used for frequency.
• Smaller time unit means faster event.
• Larger frequency unit means higher speed.
• Time Units (Ascending Order) : ps<ns<µs<ms<s
• Frequency Units (Ascending Order) : Hz<kHz<MHz<GHz<THz

[ Option A ]

In cache memory, a physical address is divided into three parts, Tag | Index (Set) | Block Offset.

• Block Offset identifies the location inside a block.
• Index bits identify the set in cache.
• Tag bits are used to check whether the required data is present in that set.

Physical Address Space = 4 GB = 2³² bytes. So, Total Address Bits = 32 bits
Block Size = 8 words and 1 word = 32 bits = 4 bytes. So, Block Size = 8*4 = 32 bytes = 2⁵. Therefore, Block Offset = 5 bits
Cache Size = 16 KB = 2¹⁴ bytes. Number of Blocks = 2¹⁴ / 2⁵ = 2⁹ = 512 blocks
Since it is 4-way Set Associative:
Number of Sets = 512 / 4 = 128 = 2⁷. Therefore, Index Bits = 7 bits
Tag Bits = Total Address Bits-(Index Bits+Offset Bits)
Tag = 32-(7+5) = 20 bits

[ Option B ]

Increasing the RAM improves system performance mainly because it reduces page faults. A page fault occurs when the required data is not found in main memory and must be fetched from secondary storage, which is much slower.

[ Option C ]

Dynamic RAM (DRAM) stores data using capacitors and needs periodic refreshing to retain data. Because of this design, DRAM consumes less power compared to Static RAM (SRAM), which uses flip-flops and consumes more power continuously. 
However, the access time of DRAM is slower than SRAM because refreshing and capacitor charging take extra time.

• The DRAM is slower, consume less power and cheaper. It is used as Main Memory.
• The SRAM is faster, consume more power and expensive. It is used in Cache.

[ Option C ]

Cache memory is a small, high-speed memory placed between the CPU and main memory. Its purpose is to reduce average memory access time by storing frequently used data.
The most important performance metric of cache memory is the Hit Ratio.
Hit Ratio = Number of cache hits / Total memory references
Cache Hit : Data is found in cache.
Cache Miss : Data is not found in cache and must be fetched from main memory.
Higher hit ratio means:

• Fewer accesses to slow main memory.
• Faster overall system performance.

[ Option D ]

In memory systems (cache memory), the Hit Rate refers to the fraction of memory accesses that are successful, meaning the required data is found in the cache.
Hit Rate = (Number of Successful Accesses) / (Total Memory Access)

Miss Rate is the fraction of memory accesses in which the required data is not found in the cache and must be fetched from main memory.
Miss Rate = (Number of Misses) / (Total Memory Access)

Note:

• Hit Rate + Miss Rate = 1
• Miss Rate = 1 - Hit Rate

[ Option B ]

The number of address lines tells us how many memory locations (words) can be addressed.
With a 12-bit address, the CPU can address: 2¹²=4096 words
The total memory capacity is given as 16 KB. 
16 KB = 16×1024 = 16384 bytes
Now, word length means the number of bytes per word. It can be calculated as:
Word Length = Total memory size (in bytes) / Number of words
Word Length = 16384 / 4096 = 4 bytes.