Memory Organization (Primary, Cache, Virtual) : MCQs & PYQs with Explanation

Option C

A memory unit stores data in the form of words. Each word contains a fixed number of bits. The total capacity of a memory is therefore defined as:
Memory Capacity=Number of words × Number of bits per word
To access and transfer data between the CPU and memory, two types of lines are used:

• Address lines which are used to select a specific memory word or location.
• Data lines which are used to transfer data to or from the selected memory word.

The Given Memory : 4K * 16
4K represents the number of words in memory : 4K = 4*1024 = 4096 Words.
16 represents the number of bits per word.
Each memory word must have a unique address. The number of address lines required depends on how many different addresses must be generated or number of memory locations (words).
Number of address lines = log₂(Number of Words)
=log₂(4096) = 12 or 4096=2¹²
The memory needs 12 address lines to uniquely identify all 4096 words.
Data lines are used to read or write one complete word at a time. Since each word contains 16 bits, the memory must have 16 data lines.

NOTE:

• Number of address lines = log₂(number of words).
• Number of data lines = decided by word size (bits per word).

Option B

A disk cache stores frequently accessed data in fast memory (RAM) to reduce slow disk I/O operations.
Hit Rate is the probability a requested data block is found in cache (40% here). Cache access time (1 ms) is much faster than disk access time (100 ms). Mean Access Time (MAT) combines both using the formula: 
MAT = (Hit Rate*Cache Time) + ((1-Hit Rate)*Disk Time)
With cache access time of 1 ms, disk access time of 100 ms, and 40% hit rate, the mean access time calculates as: 
MAT = (0.4*1)+(0.6*100) = 0.4+60 = 60.4 ms.

Option C

In computer architecture, locality of reference describes how programs access memory. One important type is spatial locality, which means that if a particular memory location is accessed, then nearby memory locations are likely to be accessed soon.
For example, when accessing elements of an array sequentially, once one element is accessed, the next nearby elements are also accessed.

Option B

An I/O processor is a special-purpose processor used to handle input and output operations independently of the CPU. Its main job is to manage data transfer between I/O devices and Main Memory.
By doing this, the I/O processor reduces the workload on the CPU and allows the CPU to continue executing other instructions while I/O operations are in progress.

Option A

SRAM (Static Random Access Memory) is the most expensive memory among SRAM, DRAM, and ERAM because it is faster, more reliable, and does not require refreshing repeatedly like DRAM.
SRAM uses more transistors for storing each bit, which increases its manufacturing cost. It is commonly used in Cache Memory.

Option A

In a RAM chip, the number of address lines determines the number of memory locations, while the number of data lines determines how many bits are stored in each location.
Here, the number of address lines is 10, so the total number of memory locations is 2¹⁰. The number of data lines is 8, which means each location can store 8 bits. Since 8 = 2³, each location stores 2³ bits.
Therefore, the total memory capacity of the RAM chip is 2¹⁰ * 2³ = 2¹³ bits.

Option A

Memory devices differ in the way data is accessed. In some memory devices, any location can be accessed directly, while in others the locations must be accessed in a specific order. The time required to access data depends on the access method used by the memory.
In Random Access memory, every memory location can be accessed directly, and the time required to access any location is almost the same. It does not matter which location was accessed previously or how far apart two locations are.

Note:

• In Random Access memory, every location can be accessed directly in the same amount of time. The access time is constant, regardless of which location is accessed.
• In Direct Access storage, data can be accessed directly without reading all previous data, but the access time is not constant. The time depends on where the data is physically located.

Option D

In a Virtual Memory system, the CPU generates addresses based on its address lines, which define the virtual address space. This virtual address space represents the range of memory addresses that a program can use, and it is not limited to the size of the physical main memory (RAM).
One of the main purposes of virtual memory is to allow programs to use an address space that is larger than the available physical memory, with the extra portion being stored on secondary storage.
However, the virtual address space cannot exceed the size of the secondary storage, because secondary storage is where the non-resident pages of memory are actually stored.
Therefore, the address space specified by the CPU must be larger than the physical memory size but smaller than the secondary storage size.

• Virtual Address Space > Physical Memory (RAM).
• Virtual Address Space < Secondary Storage (HDD).

Option C

Each RAM chip is of size 32K × 1. This means, 32K locations and 1 bit per location. So, capacity of one chip is 32K*1 bit=32K bits.
Required memory capacity : 256K bytes = 256K*8 = 2048K bits
Number of chips required : 2048K bits/32K bits per chip = 64

Option C

Cache Memory is used to store frequently accessed data so that the CPU can access it faster than main memory.
In direct mapping, each block of main memory is mapped to exactly one fixed location (line) in the cache.
This fixed mapping makes the design simple and inexpensive, but it also introduces a major drawback known as the conflict problem. 
When two or more frequently accessed main memory blocks are mapped to the same cache line, they continuously replace each other in the cache. 
As a result, even though the blocks are repeatedly used, they cannot remain in the cache simultaneously. This frequent replacement reduces the cache hit ratio and degrades overall performance.

Option C

Cache Mapping determines how memory blocks are placed in cache. In Direct Mapping, each memory block is mapped to exactly one specific cache block using a fixed formula.
In this method, consecutive memory blocks are mapped to consecutive cache blocks in a cyclic manner. This makes the mapping simple and fast.

Option D

In Cache Memory, LRU (Least Recently Used) is a replacement policy used to decide which block should be removed when a new block needs to be inserted. 
Each cache block is assigned a counter to track how recently it was used. The block with the highest counter is least recently used.
In LRU, when the requested block is not already in cache, a new block is brought in, its counter becomes 0, and the other counters are incremented. That is exactly the Miss case, not hit or write. 
The wording “a new block is identified” points to the moment a block is loaded into the cache, which happens on a Miss.

Option B

Cache Memory works effectively because of the locality of reference principle. This means that programs tend to access the same data or instructions repeatedly (Temporal Locality) or access nearby memory locations (Spatial Locality). Cache stores such frequently or recently used data, so the CPU can access it much faster than main memory.

Option B

The number of address lines depends on how many unique memory locations (words) need to be addressed. Here, the memory stores 8K words, and each word is 16 bits, but word size does not affect the number of address lines, only the number of locations matters.
So, 8K = 8*1024 = 8192 Locations. To find the number of address lines n, we use:
2ⁿ=8192
2¹³=8192
So, 13 address lines are required.

Option A

Cache Memory is a very fast memory located between the CPU and RAM. It stores frequently used data and instructions so that the CPU can access them quickly. Cache memory is usually divided into three levels:

• L1 Cache (Level 1)
• L2 Cache (Level 2)
• L3 Cache (Level 3)

The size of cache memory increases as we move from L1 to L3, L1<L2<L3. This means:

• L1 cache is the smallest.
• L2 cache is larger than L1.
• L3 cache is the largest.