ELEVATE SKILLS!
Q: 1 The characteristic equation of the T flip-flop is
T̅·Q + Q·T̅
T̅·Q + T·Q̅
TQ
T·Q̅
[ Option B ]
The characteristic equation of a flip-flop defines the next state Q(n+1) in terms of the present state Q(n) and the input. In the case of a T flip-flop, when T = 0, the output remains unchanged, meaning the next state is the same as the present state. When T = 1, the flip-flop toggles, so the next state becomes the complement of the present state.
This behavior can be expressed mathematically as: Q(n+1) = T ⊕ Q(n) which is equivalent to Q(n+1) = T·Q̅(n) + T̅·Q(n).
Q: 2 In a positive edge triggered JK flip-flop, when J=0, K=1 and Q=0, what happens to Q when the clock input goes HIGH and when the clock input goes LOW?
Q becomes 0 when the clock input is HIGH, Q becomes 0 when the clock input is LOW
Q is RESET to 1 when the clock input is LOW, Q is unchanged when the clock becomes HIGH
Q is RESET to 1 when the clock input is HIGH, Q is unchanged when the clock becomes LOW
None of the above
[ Option A ]
A positive edge triggered JK flip-flop changes its output only at the rising edge of the clock.
A rising edge (positive edge) is the moment when a digital signal changes from LOW (0) to HIGH (1).
In digital electronics, clock signals are square waves that continuously switch between 0 and 1. The transition from:
0 to 1 (LOW to HIGH) is called the Rising Edge.
1 to 0 (HIGH to LOW) is called the Falling Edge.
First, recall the JK flip-flop truth table:
| J | K | QN+1 | Operation |
|---|---|---|---|
| 0 | 0 | QN | No Change |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q’N | Toggle |
When clock goes HIGH:
Since it is positive edge triggered, the flip-flop responds only at the rising edge. At this moment, reset condition applies, so, Q becomes 0. But Q was already 0. So, it remains 0.
When clock goes LOW:
After the rising edge, the flip-flop does not respond to further clock level changes. So, Q remains unchanged (still 0).
Q: 3 Which of the following options is not true for a gated D-type flip-flop?
When clock is high, allows the input data (D) to pass through to the output (Q)
Stores a single bit of data
Uses a clock signal to control when the input data (D) is transferred to the output (Q)
When clock is low, allows the input data (D) to pass through to the output (Q)
[ Option D ]
A gated D-type flip-flop is a sequential circuit that stores one bit of data. The transfer of input D to output Q is controlled by a clock signal.
When the clock is high (1), the flip-flop becomes active and the input data D is transferred to the output Q.
When the clock is low (0), the flip-flop does not allow the input to pass through and the previous value stored in Q is maintained.
Q: 4 When does a negative level triggered flip-flop in Digital Electronics changes its state?
When the clock is Negative
When the clock is Positive
When the inputs are all zero
None of the above
[ Option A ]
A negative level triggered flip-flop is a type of flip-flop that changes its state only when the clock signal is at the low level (0). In other words, when the clock remains at a negative (low) voltage level, the flip-flop becomes active and responds to inputs.
Q: 5 Which of following circuit is used as a memory device in computer?
Flip-Flops
Rectifier
Comparator
All of these
[ Option A ]
A memory device is used to store information so that it can be used later. A Flip-Flop is a binary cell that capable of storing one bit of information. The flip-flop has two stable states either 0 called RESET or 1 called SET.
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