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  • Memory Management & Virtual Memory MCQs | Suraku Academy

Q: 1 In a paging system with a Translation Lookaside Buffer (TLB), the TLB has a hit ratio of 80%. It takes 20 nanoseconds to search the TLB and 100 nanoseconds to access main memory. What is the effective memory access time?

  1. 120 nanoseconds

  2. 140 nanoseconds

  3. 160 nanoseconds

  4. 180 nanoseconds

[ Option B ]

Q: 2 The memory allocation technique used in paging may have:

  1. External fragmentation

  2. Internal fragmentation

  3. Hybrid fragmentation

  4. No fragmentation

[ Option B ]

Paging is a memory management technique that divides physical memory into fixed-size blocks called frames and logical memory into blocks of the same size called pages. Pages are mapped to frames using a page table, allowing non-contiguous allocation of memory.

TYPE OF FRAGMENTATIONDESCRIPTION
Internal Fragmentation.Occurs when the last allocated page/frame is not fully used.
Wasted memory inside allocated blocks due to fixed-size allocation.
Paging may cause internal fragmentation because the last page of a process might not be completely filled.
External Fragmentation.Occurs when there is enough total memory to satisfy a request, but it is not contiguous.
Wasted memory outside allocated blocks due to scattered free memory.

Q: 3 In a system with a 32-bit logical address space and a page size of 4 KB approximately, how many entries are there in the page table?

  1. 220 entries

  2. 210 entries

  3. 232 entries

  4. 212 entries

[ Option A ]

In a paging system, the logical address space is divided into fixed-size pages, and a page table maps each logical page to a physical frame in memory. In this problem, the system has a 32-bit logical address space, which means it can address 232 bytes.
The page size is given as 4 KB, which is 212 bytes. To find the number of pages, we divide the total logical address space by the page size: 232/ 212=220.
Since each page requires one entry in the page table, the page table will contain 220 entries.

Q: 4 If 2n words are in main memory and 2K words are in cache memory, then the bits for tag field and index field of a n-bit memory address are respectively,

  1. n, K

  2. K, n

  3. n−K, K

  4. n+K, n

[ Option C ]

In Cache Memory, a main memory address is divided into tag, index, and block offset fields if using Direct Mapping.

  • The index field identifies the specific cache line where the memory block is stored.
  • The tag field identifies which block from main memory is stored in that cache line.

If main memory has 2n words and cache has 2K words, then:
Index field = K bits (To select one of 2K cache lines)
Tag field = n−K bits (Remaining bits to identify the memory block)

Q: 5 Which of the following describes a 32 X 8 ROM?

  1. 8 words of 32 bits each

  2. 32 words of 8 bits each

  3. 32 input lines and 8 output lines

  4. 8 input lines and 32 output lines

[ Option B ]

A Read Only Memory (ROM) is a type of non-volatile memory used to store data permanently. The notation “m × n” in memory terminology means that the ROM contains m words, and each word consists of n bits.

  • The first number (32) represents the number of memory locations (words).
  • The second number (8) represents the number of bits stored per word (i.e., output lines).

In a 32 × 8 ROM, there are 32 memory locations, and each location can store 8 bits of data. This means the ROM can store a total of 32×8=256 bits of information. Hence, a 32 × 8 ROM is best described as “32 words of 8 bits each.”

Q: 6 Consider the following memory map using multiprogram with partition model. Dark represent memory in use while white represent free memory as shown in the figure below:

65k125k150k175k150k

Request for memory follows the following order : 100k, 25k, 125k, 50k. which of the following allocation satisfies the above request?
(A)  Best Fit
(B)  First Fit
(C)  Worst Fit

  1. A, B, C

  2. A, B

  3. B, C

  4. A, C

[ Option B ]

Q: 7 Consider a system using 2-level paging and the virtual address is 38 bits. The most significant 10 bits are used to index the page directory and next 16 bits index the page table. Each entry in both levels is 4 bytes. What is the maximum size of a page table in KB?

  1. 4 KB

  2. 16 KB

  3. 256 KB

  4. None of these

[ Option C ]

The virtual address is 38 bits long, where 10 bits are for the page directory and 16 bits for the page table. Each page table entry is 4 bytes. So, the number of entries in a page table is 216. Multiplying by 4 bytes gives 218 bytes, which is equal to 256 KB. Hence, the maximum size of a page table is 256 KB.

Q: 8 What is the purpose of the valid-invalid bit in a page table entry?

  1. To track page frequency replacement

  2. To distinguish between read and write access

  3. To indicate whether the page is in physical memory

  4. To determine if the page is part of the process's logical address space

[ Option D ]

The Valid-Invalid bit in a page table entry is used to check whether a page belongs to a process’s logical address space. If the bit is valid (1), the page is part of the process and can be accessed. If it is invalid (0), the page does not belong to the process, and any access attempt will cause a memory protection error. This mechanism helps the operating system prevent illegal memory access and ensures safe process isolation.

Q: 9 Consider a logical address 0001001011110000, which representing segment number 1 (leftmost 4 bits) and offset 752. Suppose that this segment is residing in main memory starting at physical address 0010000000100000, then, the physical address of the segment is :

  1. 0010001100010000

  2. 0010001000011000

  3. 0001000101010000

  4. 0010000011011000

[ Option A ]

Q: 10 A computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average memory access time of

  1. 1100 ns

  2. 200 ns

  3. 900 ns

  4. 150 ns

[ Option B ]

Cache memory is a small, high-speed memory placed between the CPU and main memory to reduce access time. Average Memory Access Time (AMAT) is calculated using the formula:
AMAT = (Hit Ratio × Cache Access Time) + (Miss Ratio × Main Memory Access Time)

  • Hit Ratio is the fraction of memory accesses found in the cache.
  • Miss Ratio = 1 − Hit Ratio.

Given:
Cache access time = 100 ns
Main memory access time = 1000 ns
Hit ratio = 0.9
Miss Ratio=1−0.9=0.1
AMAT = (0.9×100) + (0.1×1000) = 90 + 100 = 190 ns
Approximating to the closest option gives 200 ns.

Q: 11 A condition in which a process is spending more time paging than executing is called:

  1. Race condition

  2. Thrashing

  3. Aging

  4. Virtualization

[ Option B ]

Thrashing occurs in a paging system when a process spends more time swapping pages in and out of memory than executing instructions.
It typically happens when the system does not have enough physical memory to hold the working set of all active processes. Thrashing leads to severe performance degradation, as the CPU is mostly idle waiting for page transfers.

Q: 12 What is the purpose of the free-frame list in an operating system?

  1. To track which processes are currently running

  2. To store page tables for each process

  3. To keep a list of active I/O operations

  4. To manage frames available for allocation when a page fault occurs

[ Option D ]

In an Operating System (OS) that uses virtual memory, physical memory (RAM) is divided into fixed-size blocks called frames, and logical memory is divided into pages. When a program tries to access a page that is not currently in memory, a page fault occurs.
At this time, the OS needs to bring the required page from the disk into main memory. To do this efficiently, the OS maintains a Free-Frame List, which is a list of all the empty frames available in physical memory.
When a page fault happens, the OS selects a free frame from this list, loads the required page into it, and updates the page table.

So, the free-frame list helps the operating system know which parts of memory are empty so it can quickly allocate space whenever a new page needs to be loaded due to a page fault.

Q: 13 What key principle does the LRU page replacement algorithm use to decide which page to evict?

  1. The page with the smallest page number.

  2. The page that will not be used for the longest time in the future.

  3. The page that was loaded into memory most recently.

  4. The page that has not been used for the longest period of time.

[ Option D ]

In Paging Systems, when a page fault occurs and memory is full, the OS must decide which page to replace.
LRU (Least Recently Used) algorithm evicts the page that has been unused for the longest time, under the assumption that pages used recently are more likely to be used again soon. This is based on temporal locality of reference, a key principle in memory access patterns.
So, LRU page replacement algorithm uses the principle of evicting the page that has not been used for the longest period of time.

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